LTC1645IS#TRPBF【PDF 12/24 页】IC CTRLR SEQ HOTSWAP DUAL 14SOIC

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LTC1645

1645fa

nearly unlimited current flow. The LTC1645 discharges

the GATE pin in a few microseconds, but during this

discharge time current on the order of 150 amperes flows

from the V

power supply. This current spike glitches the

power supply, causing V

to dip (Figure 8a and 8b).

On recovery from overload, some supplies may over-

shoot. Other devices attached to this supply may reset or

malfunction and the overshoot may also damage some

components. An inductor (1礖 to 10礖) in series with the

FETs source limits the short-circuit di/dt, thereby limiting

the peak current and the supply glitch (Figure 8c and 8d).

Additional power supply bypass capacitance also reduces

the magnitude of the V

glitch.

Reset

The LTC1645 uses an internal 1.238V bandgap reference,

a precision voltage comparator, and a resistive divider to

monitor the output supply voltage (Figure 9).

Whenever the voltage at the FB pin rises above its reset

threshold (1.238V), the comparator output goes high, and

a timing cycle starts (see Figure 10, time points 1 and 4).

After a complete timing cycle, RESET is released. An

external pull-up is required for the RESET pin to rise to a

logic high.

When the voltage at the FB pin drops below its reset

threshold, the comparator output goes low. After passing

through a glitch filter, RESET is pulled low (time point 2).

If the FB pin rises above the reset threshold for less than

a timing cycle, the RESET output remains low (time

point 3).

APPLICATIO S I FOR ATIO

Glitch Filter

The LTC1645 has a glitch filter to prevent RESET from

generating a spurious system reset in the presence of

transients on the FB pin. The filter is 20祍 for large

transients (greater than 150mV) and up to 80祍 for

smaller transients. The relationship between glitch filter

time and the transient voltage is shown in Typical Perfor-

mance Characteristics: Glitch Filter Time vs Feedback

Transient.

Timer

The system timing for the LTC1645 is generated by the

circuitry shown in Figure 11. The timer is used to set the

turn-on delay after the ON pin goes high. It also sets the

delay before the RESET pin goes high after the FB pin

exceeds 1.238V.

Whenever the timer is off, the internal N-channel shorts

the TIMER pin to ground (Figure 11). Activating the timer

connects a 2礎 current from V

CC1

to the TIMER pin and the

Figure 10. Supply Monitor Waveforms

Figure 9. Supply Monitor Block Diagram

Figure 11. System Timing Block Diagram

COMP

TIMER

RESET

OUT

TIMER

礟

10k

1645 F09

RESET

LOGIC

1.238V

REFERENCE

1.23V

1645 F10

OUT

TIMER

RESET

COMP

TIMER

2礎

TIMER

1.23V

SUPPLY

MONITOR

LOGIC

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